عمار جلاوي محمود كركر

Due to the exceedingly high integration density of VLSI circuits and the resulting high power density, thermal integrity became a major challenge. One way to tackle this problem is Dark silicon. Dark silicon is the amount of circuitry in a chip that is forced to switch off to insure thermal integrity of the system and prevent permanent thermal-related faults. In many-core systems, the presence of Dark Silicon adds new design constraints, in general, and on the communication fabric of such systems, in particular. This is due to the fact that system-level thermal-management systems tend to increase the distance between high activity cores to insure better thermal balancing and integrity. Consequently, a designing dilemma is created where a compromise has to be made between interconnect performance and power consumption. This study proposes a hybrid wire and surface-wave interconnect (SWI) based Network-on-Chip (NoC) to address the dark silicon challenge. Through efficient utilization of one-hop cross the chip communication SWI links, the proposed architecture is able to offer an efficient and scalable communication platform in terms of performance, power, and thermal impact. As a result, evaluations of the proposed architecture compared to baseline architecture under dark silicon scenarios show reduction in maximum temperature by 15∘C, average delay up to 73.1%, and energy-saving up to ∼3X. This study explores the promising potential of the proposed architecture in extending the utilization wall for current and future many-core systems in dark silicon era.

In the era of many-core chips, the problem of power density is a serious challenge. This is particularly important in Network-on-Chip (NoC)-based systems, where application mapping determines the resulting power patterns and the workload distribution across the entire chip. Despite this fact, the majority of mapping algorithms focus on performance, and the resulting power patterns are largely ignored. This work investigates this problem. Three different power pattern metrics with different scopes are defined, namely, power peak, power range, and regional power density. The results of using them as mapping objectives together with communication cost using a multi-objective evolutionary mapping approach are investigated. Results show that employing power patterns results-in Pareto fronts with different power patterns and features. Results are analysed and discussed. Moreover, a case study of thermal analysis

Electronic learning (e‑learning) plays a significant role in improving the efficiency of the education process. However, in many cases in developing countries, technology transfer without consideration of technology acceptance factors has limited the impact of e‑learning and the expected outcome of the education process. Therefore, this shift in learning method has been met with low enthusiasm from academic staff and students owing to its low perceived usefulness and perceived ease‑of‑use. The University of Kufa (UoK) in Iraq is considered a good case study because it has implemented the e‑learning platform since 2013. The UoK platform is based on open‑source Moodle owing to the latter’s advantages, such as low implementation cost, open community for support and continuous update and development. To identify and evaluate the challenges, this study uses a questionnaire survey that targets the level of adoption, implementation, familiarity and technology acceptance of staff and students. A total of 242 educators participate in the survey, and the data are subsequently analysed. Important information is extracted using data mining techniques, namely clustering and decision trees. One of the main crucial factors extracted from the analysis results is the perception that social media is easier to use compared with a dedicated e‑learning platform such as Moodle. This factor may also discourage educators/learners from adopting an offered e‑learning platform, regardless of actual usefulness, motivation and training programs.

Networks-on-chip (NoC) has been proven to satisfy different on-chip communication requirements in terms of costs, performance, and reliabilities. This has been proven true especially for spiking neural network (SNN) with its high multicast communication demands. However, metal-wires that form the foundation for regular NoCs face a set of challenges since metal-wires have been stretched to their physical limits with the relentless technology scaling. Thus, this paper tackles SNN communication issues on two fronts: Firstly, the physical interconnect layer by attempting to prototyping a new and promising type of wireless interconnects called surface-wave interconnects (SWI). Secondly, the architectural level by proposing NoC architecture enabled by SWI and further more effective for multicast communication. A surface-wave has been demonstrated for range 14-25 GHz with improvements over free-space propagation in S21 up to 20 dB. Furthermore, based on this technology a hybrid wire and surface-wave architecture is developed and evaluated to demonstrate its potentials for SNN, which found to perform 95% better than related-work. Consequently, this emerging technology would provide the high efficiency that are required for future NoC-based SNN systems.

Networks-on-chip (NoC) have emerged to tackle different on-chip communication challenges and can satisfy different demands in terms of performance, cost and reliability. Currently, interconnects based on metal are reaching performance limits given relentless technology scaling. In particular, a performance bottleneck has emerged due to the demands for communication in terms of bandwidth for multicasting and broadcasting. As a result, various state-of-the-art architectures have been proposed as alternatives and emerging interconnects including the use of optics or radio frequency (RF). This article presents a comprehensive survey of these various interconnect fabrics, and discusses their current and future potentials and obstacles as well. This article aims to drive the research community to achieve a better utilization of the merits of on-chip interconnects and addresses the challenges involved. New interconnect technologies, such as optical interconnect, wireless NoC (WiNoC), RF transmission lines (RF-I) and surface wave interconnects (SWI), are discussed, evaluated and compared. Consequently, these emerging interconnects can continue to provide the cost efficiency and performance that are highly demanded for future many-core processors and high performance computing.

The network-on-chip (NoC) has been introduced as an efficient communication backbone to tackle the increasing challenges of on-chip communication. Nevertheless, merely metalbased NoC implementation offers only limited performance and power scalability in terms of multicast and broadcast traffics. To meet scalability demands, this paper addresses the systemlevel challenges for intra-chip multicast communication in a proposed hybrid interconnects architecture. This hybrid NoC combines and utilizes both regular metal on-chip interconnects and new type of wireless-NoC (WiNoC) which is Zenneck surface wave interconnects (SWI). Moreover, this paper embeds novel multicast routing and arbitration schemes to address system-level multicast-challenges in the proposed architecture. Specifically, a design exploration of contention handling in SWI layer is considered in both centralized and decentralized manners. Consequently, the hybrid wire-SWI architecture avoids overloading the network, alleviates the formation of traffic hotspots and avoid deadlocks that are typically associated with state-of-theart multicast handling. The evaluation is based on a cycleaccurate simulation and hardware description. It demonstrates the effectiveness of the proposed architecture in terms of power consumption (up to around 10x) and performance (around 22x) compared to regular NoCs. These results are achieved with negligible hardware overheads. This study explore promising potential of the proposed architecture for current and future NoC-based many-core processors.

حصل م.د. عمار جلاوي على منحة فولبرايت للاستاذ الزائر لصيف عام 2019 والذي يهدف الى تطوير المهارات البحثية والتدريسيية للباحثيين العراقيين في الاختصاصات الهندسية. حيث كان من ضمن مجموعة تتالف من 7 اكاديميين من مختلف جامعات العراق والاختصاصات.

القاء كورس في مركز ابن سينا عن طريقة تحضير والقاء البحوث في المؤتمرات والمحافل العلمية

القاء محاضرتين عن الانظمة المدمجة ذات المعالجات المتعددة ومحاضرة عن FPGA

بناءا على الدعوة من قبل البروفسور ماك قام م.د. عمار جلاوي بزيارة جامعة ساوث امبتون والقاء السمينار العلمي حول اخر بحوثه في مجال الشبكات في داخل الرقاقات الالكترونية وتم بعدها التحاول حول سبل تطوير البحث والتعاون العلمي

ام م.د. عمار جلاوي محمود الباحث في مركز البحث والتاهيل المعلوماتي بالمشاركة في مؤتمر العلمي تكلوجيا المعلومات والاتصالات المقام تحت شعار التطبيقات الحديثة لتكنلوجيا المعلومات والاتصالات والمدعوم من قبل مؤسسة IEEE الامريكية ببحثه المعنون "Efficient Surface-wave-based Network-on-chip Architecture for Spiking-neural-network"